Information

Table 10-27. UART 1 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART1_CTS CTS Clear to send I
UART1_RTS RTS Request to send O
UART1_TX TXD Transmit data O
UART1_RX RXD Receive data I
Table 10-28. UART 2 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART2_CTS CTS Clear to send I
UART2_RTS RTS Request to send O
UART2_TX TXD Transmit data O
UART2_RX RXD Receive data I
Table 10-29. UART 3 Signal Descriptions
Chip signal name Module signal
name
Description I/O
UART3_CTS CTS Clear to send I
UART3_RTS RTS Request to send O
UART3_TX TXD Transmit data O
UART3_RX RXD Receive data I
Table 10-30. SDHC Signal Descriptions
Chip signal name Module signal
name
Description I/O
SDHC0_DCLK SDHC_DCLK Generated clock used to drive the MMC, SD, SDIO or CE-ATA
cards.
O
SDHC0_CMD SDHC_CMD Send commands to and receive responses from the card. I/O
SDHC0_D0 SDHC_D0 DAT0 line or busy-state detect I/O
SDHC0_D1 SDHC_D1 8-bit mode: DAT1 line
4-bit mode: DAT1 line or interrupt detect
1-bit mode: Interrupt detect
I/O
SDHC0_D2 SDHC_D2 4-/8-bit mode: DAT2 line or read wait
1-bit mode: Read wait
I/O
SDHC0_D3 SDHC_D3 4-/8-bit mode: DAT3 line or configured as card detection pin
1-bit mode: May be configured as card detection pin
I/O
Chapter 10 Signal Multiplexing and Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 235