Information

Section Number Title Page
28.4.10 FTFL Command Description.......................................................................................................................626
28.4.11 Security........................................................................................................................................................648
28.4.12 Reset Sequence............................................................................................................................................650
Chapter 29
External Bus Interface (FlexBus)
29.1 Introduction...................................................................................................................................................................651
29.1.1 Overview......................................................................................................................................................651
29.1.2 Features........................................................................................................................................................651
29.1.3 Modes of Operation.....................................................................................................................................652
29.2 Signal Descriptions.......................................................................................................................................................652
29.2.1 Address and Data Buses (FB_An, FB_Dn, FB_ADn).................................................................................653
29.2.2 Chip Selects (FB_CS[5 :0]).........................................................................................................................653
29.2.3 Byte Enables (FB_BE_31_24, FB_BE_23_16, FB_BE_15_8, FB_BE_7_0).............................................654
29.2.4 Output Enable (FB_OE)...............................................................................................................................654
29.2.5 Read/Write (FB_R/W).................................................................................................................................654
29.2.6 Transfer Start/Address Latch Enable (FB_TS/FB_ALE)............................................................................654
29.2.7 Transfer Size (FB_TSIZ[1:0]).....................................................................................................................655
29.2.8 Transfer Burst (FB_TBST)..........................................................................................................................655
29.2.9 Transfer Acknowledge (FB_TA).................................................................................................................656
29.3 Memory Map/Register Definition.................................................................................................................................656
29.3.1 Chip select address register (FB_CSARn)...................................................................................................658
29.3.2 Chip select mask register (FB_CSMRn)......................................................................................................659
29.3.3 Chip select control register (FB_CSCRn)....................................................................................................660
29.3.4 Chip select port multiplexing control register (FB_CSPMCR)...................................................................663
29.4 Functional Description..................................................................................................................................................664
29.4.1 Chip-Select Operation..................................................................................................................................664
29.4.2 Data Transfer Operation...............................................................................................................................666
29.4.3 Data Byte Alignment and Physical Connections.........................................................................................666
29.4.4 Address/Data Bus Multiplexing...................................................................................................................667
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
24 Freescale Semiconductor, Inc.