Information

Section Number Title Page
29.4.5 Bus Cycle Execution....................................................................................................................................668
29.4.6 FlexBus Timing Examples...........................................................................................................................670
29.4.7 Burst Cycles.................................................................................................................................................688
29.4.8 Extended Transfer Start/Address Latch Enable...........................................................................................697
29.4.9 Bus Errors....................................................................................................................................................697
29.5 Initialization/Application Information..........................................................................................................................698
29.5.1 Initializing a Chip Select..............................................................................................................................698
29.5.2 Reconfiguring a Chip Select........................................................................................................................698
Chapter 30
EzPort
30.1 Overview.......................................................................................................................................................................699
30.1.1 Introduction..................................................................................................................................................699
30.1.2 Features........................................................................................................................................................700
30.1.3 Modes of Operation.....................................................................................................................................700
30.2 External Signal Description..........................................................................................................................................701
30.2.1 EzPort Clock (EZP_CK)..............................................................................................................................701
30.2.2 EzPort Chip Select (EZP_CS)......................................................................................................................701
30.2.3 EzPort Serial Data In (EZP_D)....................................................................................................................702
30.2.4 EzPort Serial Data Out (EZP_Q).................................................................................................................702
30.3 Command Definition....................................................................................................................................................702
30.3.1 Command Descriptions................................................................................................................................703
30.4 Flash Memory Map for EzPort Access.........................................................................................................................707
Chapter 31
Cyclic redundancy check (CRC)
31.1 Introduction...................................................................................................................................................................709
31.1.1 Features........................................................................................................................................................709
31.1.2 Block diagram..............................................................................................................................................709
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 25