Information

SIM_SOPT2 field descriptions (continued)
Field Description
10 OSCERCLK clock
11 External bypass clock (I2S0_CLKIN)
23–22
Reserved
This read-only field is reserved and always has the value zero.
21–20
Reserved
This read-only field is reserved and always has the value zero.
19
Reserved
This read-only field is reserved and always has the value zero.
18
USBSRC
USB clock source select
Selects the clock source for the USB 48 MHz clock.
0 External bypass clock (USB_CLKIN).
1 MCGPLLCLK/MCGFLLCLK clock divided by the USB fractional divider. See the
SIM_CLKDIV2[USBFRAC, USBDIV] descriptions.
17
Reserved
This read-only field is reserved and always has the value zero.
16
PLLFLLSEL
PLL/FLL clock select
Selects the MCGPLLCLK or MCGFLLCLK clock for various peripheral clocking options.
0 MCGFLLCLK clock
1 MCGPLLCLK clock
15–13
Reserved
This read-only field is reserved and always has the value zero.
12
TRACECLKSEL
Debug trace clock select
Selects the core/system clock or MCG output clock (MCGOUTCLK) as the trace clock source.
0 MCGOUTCLK
1 Core/system clock
11
CMTUARTPAD
CMT/UART pad drive strength
Controls the output drive strength of the CMT IRO signal or UART0_TXD signal on PTD7 pin by selecting
either one or two pads to drive it.
0 Single-pad drive strength for CMT IRO or UART0_TXD.
1 Dual-pad drive strength for CMT IRO or UART0_TXD.
10
Reserved
This read-only field is reserved and always has the value zero.
9–8
FBSL
FlexBus security level
If flash security is enabled, then this field affects what CPU operations can access off-chip via the FlexBus
interface. This field has no effect if flash security is not enabled.
00 All off-chip accesses (instruction and data) via the FlexBus are disallowed.
01 All off-chip accesses (instruction and data) via the FlexBus are disallowed.
Table continues on the next page...
Chapter 12 System integration module (SIM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 263