Information
Section Number Title Page
32.3.8 ADC offset correction register (ADCx_OFS)..............................................................................................737
32.3.9 ADC plus-side gain register (ADCx_PG)....................................................................................................738
32.3.10 ADC minus-side gain register (ADCx_MG)...............................................................................................738
32.3.11 ADC plus-side general calibration value register (ADCx_CLPD)..............................................................739
32.3.12 ADC plus-side general calibration value register (ADCx_CLPS)...............................................................740
32.3.13 ADC plus-side general calibration value register (ADCx_CLP4)...............................................................740
32.3.14 ADC plus-side general calibration value register (ADCx_CLP3)...............................................................741
32.3.15 ADC plus-side general calibration value register (ADCx_CLP2)...............................................................741
32.3.16 ADC plus-side general calibration value register (ADCx_CLP1)...............................................................742
32.3.17 ADC plus-side general calibration value register (ADCx_CLP0)...............................................................742
32.3.18 ADC PGA register (ADCx_PGA)...............................................................................................................743
32.3.19 ADC minus-side general calibration value register (ADCx_CLMD)..........................................................744
32.3.20 ADC minus-side general calibration value register (ADCx_CLMS)..........................................................745
32.3.21 ADC minus-side general calibration value register (ADCx_CLM4)...........................................................745
32.3.22 ADC minus-side general calibration value register (ADCx_CLM3)...........................................................746
32.3.23 ADC minus-side general calibration value register (ADCx_CLM2)...........................................................746
32.3.24 ADC minus-side general calibration value register (ADCx_CLM1)...........................................................747
32.3.25 ADC minus-side general calibration value register (ADCx_CLM0)...........................................................747
32.4 Functional description...................................................................................................................................................748
32.4.1 PGA functional description..........................................................................................................................748
32.4.2 Clock select and divide control....................................................................................................................749
32.4.3 Voltage reference selection..........................................................................................................................749
32.4.4 Hardware trigger and channel selects..........................................................................................................750
32.4.5 Conversion control.......................................................................................................................................751
32.4.6 Automatic compare function........................................................................................................................758
32.4.7 Calibration function.....................................................................................................................................759
32.4.8 User defined offset function.........................................................................................................................761
32.4.9 Temperature sensor......................................................................................................................................762
32.4.10 MCU wait mode operation...........................................................................................................................762
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 27