Information

12.2.10 System Clock Gating Control Register 3 (SIM_SCGC3)
Address: SIM_SCGC3 is 4004_7000h base + 1030h offset = 4004_8030h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 0 0
ADC1
0
FTM2
0
SDHC
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0 0
FLEXCAN1
0 0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_SCGC3 field descriptions
Field Description
31
Reserved
This read-only field is reserved and always has the value zero.
30
Reserved
This read-only field is reserved and always has the value zero.
29–28
Reserved
This read-only field is reserved and always has the value zero.
27
ADC1
ADC1 Clock Gate Control
This bit controls the clock gate to the ADC1 module.
0 Clock disabled
1 Clock enabled
26–25
Reserved
This read-only field is reserved and always has the value zero.
24
FTM2
FTM2 Clock Gate Control
This bit controls the clock gate to the FTM2 module.
0 Clock disabled
1 Clock enabled
23–18
Reserved
This read-only field is reserved and always has the value zero.
17
SDHC
SDHC Clock Gate Control
This bit controls the clock gate to the SDHC module.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
274 Freescale Semiconductor, Inc.