Information

SIM_SCGC3 field descriptions (continued)
Field Description
0 Clock disabled
1 Clock enabled
16–13
Reserved
This read-only field is reserved and always has the value zero.
12
Reserved
This read-only field is reserved and always has the value zero.
11–5
Reserved
This read-only field is reserved and always has the value zero.
4
FLEXCAN1
FlexCAN1 Clock Gate Control
This bit controls the clock gate to the FlexCAN1 module.
0 Clock disabled
1 Clock enabled
3–1
Reserved
This read-only field is reserved and always has the value zero.
0
Reserved
This read-only field is reserved and always has the value zero.
12.2.11 System Clock Gating Control Register 4 (SIM_SCGC4)
Address: SIM_SCGC4 is 4004_7000h base + 1034h offset = 4004_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0 1
LLWU
0
VREF
CMP
USBOTG
0
W
Reset
0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
UART3 UART2 UART1 UART0
0
I2C1 I2C0
1 0
CMT
EWM
0
W
Reset
0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0
SIM_SCGC4 field descriptions
Field Description
31
Reserved
This read-only field is reserved and always has the value zero.
30–29
Reserved
This read-only field is reserved and always has the value one.
Table continues on the next page...
Chapter 12 System integration module (SIM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 275