Information

SIM_SCGC4 field descriptions (continued)
Field Description
28
LLWU
LLWU Clock Gate Control
This bit controls the clock gate to the LLWU module.
0 Clock disabled
1 Clock enabled
27–21
Reserved
This read-only field is reserved and always has the value zero.
20
VREF
VREF Clock Gate Control
This bit controls the clock gate to the VREF module.
0 Clock disabled
1 Clock enabled
19
CMP
Comparator Clock Gate Control
This bit controls the clock gate to the comparator module.
0 Clock disabled
1 Clock enabled
18
USBOTG
USB Clock Gate Control
This bit controls the clock gate to the USB module.
0 Clock disabled
1 Clock enabled
17–14
Reserved
This read-only field is reserved and always has the value zero.
13
UART3
UART3 Clock Gate Control
This bit controls the clock gate to the UART3 module.
0 Clock disabled
1 Clock enabled
12
UART2
UART2 Clock Gate Control
This bit controls the clock gate to the UART2 module.
0 Clock disabled
1 Clock enabled
11
UART1
UART1 Clock Gate Control
This bit controls the clock gate to the UART1 module.
0 Clock disabled
1 Clock enabled
10
UART0
UART0 Clock Gate Control
This bit controls the clock gate to the UART0 module.
Table continues on the next page...
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
276 Freescale Semiconductor, Inc.