Information

SIM_SCGC6 field descriptions (continued)
Field Description
12
SPI0
SPI0 Clock Gate Control
This bit controls the clock gate to the SPI0 module.
0 Clock disabled
1 Clock enabled
11–5
Reserved
This read-only field is reserved and always has the value zero.
4
FLEXCAN0
FlexCAN0 Clock Gate Control
This bit controls the clock gate to the FlexCAN0 module.
0 Clock disabled
1 Clock enabled
3–2
Reserved
This read-only field is reserved and always has the value zero.
1
DMAMUX
DMA Mux Clock Gate Control
This bit controls the clock gate to the DMA Mux module.
0 Clock disabled
1 Clock enabled
0
FTFL
Flash Memory Clock Gate Control
This bit controls the clock gate to the flash memory.
0 Clock disabled
1 Clock enabled
12.2.14 System Clock Gating Control Register 7 (SIM_SCGC7)
Address: SIM_SCGC7 is 4004_7000h base + 1040h offset = 4004_8040h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MPU DMA
FLEXBUS
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
282 Freescale Semiconductor, Inc.