Information

12.2.16 System Clock Divider Register 2 (SIM_CLKDIV2)
Address: SIM_CLKDIV2 is 4004_7000h base + 1048h offset = 4004_8048h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
I2SDIV
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
I2SFRAC
0
USBDIV
USBFRAC
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SIM_CLKDIV2 field descriptions
Field Description
31–20
I2SDIV
I2S clock divider value
This field sets the divide value for when the fractional clock divider is used as the source for the I
2
S
master clock. The clock input to the fractional clock divider is set by the SOPT2[I2SSRC] bit.
Divider output clock = Divider input clock × [(I2SFRAC+1) / (I2SDIV+1) ]
NOTE: The I2S clock must be disabled (SCGC6[I2S] = 0) before altering this bitfield.
19–16
Reserved
This read-only field is reserved and always has the value zero.
15–8
I2SFRAC
I2S clock divider fraction
This field sets the multiply value for when the fractional clock divider is used as a the source for I
2
S
master clock. The clock input to the fractional clock divider is set by the SOPT2[I2SSRC] bit.
Divider output clock = Divider input clock × [(I2SFRAC+1) / (I2SDIV+1) ]
NOTE: The I2S clock must be disabled (SCGC6[I2S] = 0) before altering this bitfield.
7–4
Reserved
This read-only field is reserved and always has the value zero.
3–1
USBDIV
USB clock divider divisor
This field sets the divide value for the fractional clock divider when the MCGFLLCLK/MCGPLLCLK clock
is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
0
USBFRAC
USB clock divider fraction
This field sets the fraction multiply value for the fractional clock divider when the MCGFLLCLK/
MCGPLLCLK clock is the USB clock source (SOPT2[USBSRC] = 1).
Divider output clock = Divider input clock × [ (USBFRAC+1) / (USBDIV+1) ]
Memory map and register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
286 Freescale Semiconductor, Inc.