Information

Wait
Stop
Run
LLS
VLLS
3, 2, 1
VLPS
VLPR
VLPW
Any reset
4
6
7
3
1
2
8
10
11
9
5
Figure 13-1. Power Mode State Diagram
The following table defines triggers for the various state transitions shown in the previous
figure.
Table 13-2. Power mode transition triggers
Transition # From To Trigger Conditions
1 Run Wait Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, controlled in System Control Register in ARM core.
Wait Run Interrupt or Reset
2 Run STOP Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, controlled in System Control Register in ARM core
STOP Run Interrupt or Reset
Table continues on the next page...
Introduction
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
296 Freescale Semiconductor, Inc.