Information

Table 13-2. Power mode transition triggers (continued)
Transition # From To Trigger Conditions
3 Run VLPR Reduce system, bus and core frequency to 2 MHz or less,
Flash access limited to 1MHz.
AVLP=1,
Set RUNM = 10.
NOTE: Poll VLPRS bit before transitioning out of VLPR
mode.
VLPR Run Set RUNM = 00 or
Interrupt with LPWUI =1 or
Reset.
NOTE: Poll REGONS bit before increasing frequency.
4 VLPR VLPW Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
clear, controlled in System Control Register in ARM core
VLPW VLPR Interrupt with LPWUI = 0
5 VLPW Run Interrupt with LPWUI = 1 or
Reset
6 VLPR VLPS LPLLSM=000 or 010, Sleep-now or sleep-on-exit modes
entered with SLEEPDEEP set, controlled in System Control
Register in ARM core
VLPS VLPR Interrupt with LPWUI = 0
7 Run VLPS AVLP=1, LPLLSM=010, Sleep-now or sleep-on-exit modes
entered with SLEEPDEEP set, controlled in System Control
Register in ARM core
NOTE: Hardware will set LPWUI and will remain set until
software clears.
VLPS Run Interrupt with LPWUI =1 or
Reset
8 Run LLS LPLLSM=011, Sleep-now or sleep-on-exit modes entered
with SLEEPDEEP set, controlled in System Control Register
in ARM core
LLS Run Wakeup from enabled LLWU input source or RESET pin
9 VLPR LLS LPLLSM=011, Sleep-now or sleep-on-exit modes entered
with SLEEPDEEP set, controlled in System Control Register
in ARM core
10 Run VLLS(3,2,1) LPLLSM = (see PMCTRL register description for VLLS
configuration),
Sleep-now or sleep-on-exit modes entered with SLEEPDEEP
set, controlled in System Control Register in ARM core
VLLS(3,2,1) Run Wakeup from enabled LLWU input source or RESET pin
Table continues on the next page...
Chapter 13 Mode Controller
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 297