Information

Section Number Title Page
35.1.4 VREF Signal Descriptions...........................................................................................................................819
35.2 Memory Map and Register Definition..........................................................................................................................819
35.2.1 VREF Trim Register (VREF_TRM)............................................................................................................820
35.2.2 VREF Status and Control Register (VREF_SC)..........................................................................................821
35.3 Functional Description..................................................................................................................................................822
35.3.1 Voltage Reference Disabled, SC[VREFEN] = 0.........................................................................................822
35.3.2 Voltage Reference Enabled, SC[VREFEN] = 1..........................................................................................822
35.4 Initialization/Application Information..........................................................................................................................823
Chapter 36
Programmable Delay Block (PDB)
36.1 Introduction...................................................................................................................................................................825
36.1.1 Features........................................................................................................................................................825
36.1.2 Implementation............................................................................................................................................826
36.1.3 Back-to-back Acknowledgement Connections............................................................................................827
36.1.4 DAC External Trigger Input Connections...................................................................................................827
36.1.5 Block Diagram.............................................................................................................................................827
36.1.6 Modes of Operation.....................................................................................................................................829
36.2 PDB Signal Descriptions..............................................................................................................................................829
36.3 Memory Map and Register Definition..........................................................................................................................829
36.3.1 Status and Control Register (PDBx_SC).....................................................................................................831
36.3.2 Modulus Register (PDBx_MOD).................................................................................................................833
36.3.3 Counter Register (PDBx_CNT)...................................................................................................................834
36.3.4 Interrupt Delay Register (PDBx_IDLY)......................................................................................................834
36.3.5 Channel n Control Register 1 (PDBx_CHnC1)...........................................................................................835
36.3.6 Channel n Status Register (PDBx_CHnS)...................................................................................................836
36.3.7 Channel n Delay 0 Register (PDBx_CHnDLY0)........................................................................................837
36.3.8 Channel n Delay 1 Register (PDBx_CHnDLY1)........................................................................................837
36.3.9 DAC Interval Trigger n Control Register (PDBx_DACINTCn).................................................................838
36.3.10 DAC Interval n Register (PDBx_DACINTn)..............................................................................................838
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
30 Freescale Semiconductor, Inc.