Information

Address: LLWU_CS is 4007_C000h base + 8h offset = 4007_C008h
Bit 7 6 5 4 3 2 1 0
Read ACKISO 0
FLTEP FLTR
Write w1c 1
Reset
0 0 0 0 0 1 0 0
LLWU_CS field descriptions
Field Description
7
ACKISO
Acknowledge Isolation
Reading this bit indicates whether certain peripherals and the I/O pads are in a latched state as a result of
having been in a VLLS mode. Writing one to this bit when it is set releases the I/O pads and certain
peripherals to their normal run mode state.
0 Peripherals and I/O pads are in normal run state
1 Certain peripherals and I/O pads are in an isolated and latched state
6–3
Reserved
This read-only field is reserved and always has the value zero.
2
Reserved
This field is reserved.
1
FLTEP
Digital Filter on External Pin
Enables the digital filter for the external pin detect.
0 Filter not enabled
1 Filter enabled
0
FLTR
Digital Filter on RESET Pin
Enables the digital filter for the RESET pin during LLS and VLLS modes.
0 Filter not enabled
1 Filter enabled
15.4 Functional description
This on-chip peripheral module is called a low leakage wake up (LLWU) module
because it allows internal peripherals and external input pins to be sources of wakeup
from low leakage modes. It is only operational in LLS and VLLS modes.
The LLWU module contains pin enables for each external pin and internal module. For
each external pin, the user can disable or select the edge type for the wakeup. Choices are
falling, rising or either edge (any change). When an external pin is enabled as a wakeup
source the pin must be configured as an input pin.
Chapter 15 Low-leakage wake-up unit (LLWU)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 337