Information

The LLWU implements an optional 3-cycle glitch filter, based on the LPO clock, such
that a detected external pin is required to stay asserted until the enabled glitch filter times
out. There is also 2 additional cycles of latency due to synchronization that results in a
total of 5 cycles of delay before the detect circuit alerts the system to the wakeup or reset
event when the filter function is enabled. The wakeup detect glitch filter is implemented
on the "OR" of external pin inputs of all enabled external pins. There is separate reset
glitch filter implemented on the RESET pin. There is no glitch filtering on the internal
modules.
NOTE
The wakeup glitch filter should not be enabled if any of the
external pin detect edge types is set for either edge. Enabling
the wakeup glitch filter and selecting either edge detect on any
pin results in unpredictable operation.
For internal module wakeup operation, the WUMEx bit enables the respective module as
a wakeup source.
15.4.1 LLS mode
While in LLS, the MCU is in a state retention mode where all registers and memory
retains its contents. The I/O pins are held in their input or output state. Upon wakeup, the
power management control (PMC) is re-enabled, goes through a power up sequence to
full regulation and releases the logic from state retention mode. The I/O states are
released. Wakeup events triggered from either an external pin input or an internal module
input result in a CPU interrupt flow to begin user code execution.
An LLS reset event due to RESET pin assertion causes an exit via a system reset. State
retention data is lost, the I/O states return to their reset state, and the ACKISO bit is not
set. The MC_SRS[WAKEUP] and MC_SRS[PIN] bits are set and the system executes a
reset flow before CPU operation begins with a reset vector fetch.
15.4.2 VLLS modes
While in VLLS, much of the internal digital logic is powered down. The I/O pins are held
in their input or output state. Refer to the device's Power Management chapter for
powered and un-powered modules in VLLSx modes. After wakeup or reset, the PMC is
re-enabled and performs a power-up sequence to full regulation.
Functional description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
338 Freescale Semiconductor, Inc.