Information

MCM memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
E008_000A
Crossbar switch (AXBS) master configuration
(MCM_PLAMC)
16 R 003Fh 16.2.2/342
E008_000C SRAM arbitration and protection (MCM_SRAMAP) 32 R/W 0000_0000h 16.2.3/343
E008_0010 Interrupt status register (MCM_ISR) 32 R 0000_0000h 16.2.4/344
E008_0014 ETB counter control register (MCM_ETBCC) 32 R/W 0000_0000h 16.2.5/345
E008_0018 ETB reload register (MCM_ETBRL) 32 R/W 0000_0000h 16.2.6/346
E008_001C ETB counter value register (MCM_ETBCNT) 32 R 0000_0000h 16.2.7/347
16.2.1 Crossbar switch (AXBS) slave configuration (MCM_PLASC)
The PLASC is a 16-bit read-only register identifying the presence/absence of bus slave
connections to the device’s crossbar switch.
Address: MCM_PLASC is E008_0000h base + 8h offset = E008_0008h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 ASC
Write
Reset
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
MCM_PLASC field descriptions
Field Description
15–8
Reserved
This read-only field is reserved and always has the value zero.
7–0
ASC
Each bit in the ASC field indicates if there is a corresponding connection to the crossbar switch's slave
input port.
0 A bus slave connection to AXBS input port n is absent
1 A bus slave connection to AXBS input port n is present
16.2.2 Crossbar switch (AXBS) master configuration (MCM_PLAMC)
The PLAMC is a 16-bit read-only register identifying the presence/absence of bus master
connections to the device's crossbar switch.
Address: MCM_PLAMC is E008_0000h base + Ah offset = E008_000Ah
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Read 0 AMC
Write
Reset
0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
Memory Map/Register Descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
342 Freescale Semiconductor, Inc.