Information

MCM_PLAMC field descriptions
Field Description
15–8
Reserved
This read-only field is reserved and always has the value zero.
7–0
AMC
Each bit in the AMC field indicates if there is a corresponding connection to the AXBS master input port.
0 A bus master connection to AXBS input port n is absent
1 A bus master connection to AXBS input port n is present
16.2.3 SRAM arbitration and protection (MCM_SRAMAP)
The SRAMAP register defines the arbitration and protection schemes for the two SRAM
arrays.
NOTE
Bits 23-0 are undefined after reset.
Address: MCM_SRAMAP is E008_0000h base + Ch offset = E008_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
SRAMLWP
SRAMLAP
0
SRAMUWP
SRAMUAP Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
Reserved Reserved
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MCM_SRAMAP field descriptions
Field Description
31
Reserved
This read-only field is reserved and always has the value zero.
30
SRAMLWP
SRAM_L write protect
When this bit is set, writes to SRAM_L array generates a bus error.
29–28
SRAMLAP
SRAM_L arbitration priority
Defines the arbitration scheme and priority for the processor and SRAM backdoor accesses to the
SRAM_L array.
00 Round robin
Table continues on the next page...
Chapter 16 Miscellaneous Control Module (MCM)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 343