Information

MPU_RGDn_WORD2 field descriptions (continued)
Field Description
0 Bus master 4 reads terminate with an access error and the read is not performed
1 Bus master 4 reads allowed
24
M4WE
Bus master 4 write enable
0 Bus master 4 writes terminate with an access error and the write is not performed
1 Bus master 4 writes allowed
23
Reserved
This field is reserved.
This bit must be written with a zero.
22–21
M3SM
Bus master 3 supervisor mode access control
Defines the access controls for bus master 3 in supervisor mode
00 r/w/x; read, write and execute allowed
01 r/x; read and execute allowed, but no write
10 r/w; read and write allowed, but no execute
11 Same as user mode defined in M3UM
20–18
M3UM
Bus master 3 user mode access control
Defines the access controls for bus master 3 in user mode. M3UM consists of three independent bits,
enabling read (r), write (w), and execute (x) permissions.
0 An attempted access of that mode may be terminated with an access error (if not allowed by another
descriptor) and the access not performed.
1 Allows the given access type to occur
17
Reserved
This field is reserved.
This bit must be written with a zero.
16–15
M2SM
Bus master 2 supervisor mode access control
See M3SM description
14–12
M2UM
Bus master 2 user mode access control
See M3UM description
11
Reserved
This field is reserved.
This bit must be written with a zero.
10–9
M1SM
Bus master 1 supervisor mode access control
See M3SM description
8–6
M1UM
Bus master 1 user mode access control
See M3UM description
5
Reserved
This field is reserved.
This bit must be written with a zero.
4–3
M0SM
Bus master 0 supervisor mode access control
See M3SM description
2–0
M0UM
Bus master 0 user mode access control
Table continues on the next page...
Chapter 18 Memory Protection Unit (MPU)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 375