Information

AIPS memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_0040 Peripheral Access Control Register (AIPS0_PACRE) 32 R/W Undefined 19.2.3/396
4000_0044 Peripheral Access Control Register (AIPS0_PACRF) 32 R/W Undefined 19.2.3/396
4000_0048 Peripheral Access Control Register (AIPS0_PACRG) 32 R/W Undefined 19.2.3/396
4000_004C Peripheral Access Control Register (AIPS0_PACRH) 32 R/W Undefined 19.2.3/396
4000_0050 Peripheral Access Control Register (AIPS0_PACRI) 32 R/W Undefined 19.2.3/396
4000_0054 Peripheral Access Control Register (AIPS0_PACRJ) 32 R/W Undefined 19.2.3/396
4000_0058 Peripheral Access Control Register (AIPS0_PACRK) 32 R/W Undefined 19.2.3/396
4000_005C Peripheral Access Control Register (AIPS0_PACRL) 32 R/W Undefined 19.2.3/396
4000_0060 Peripheral Access Control Register (AIPS0_PACRM) 32 R/W Undefined 19.2.3/396
4000_0064 Peripheral Access Control Register (AIPS0_PACRN) 32 R/W Undefined 19.2.3/396
4000_0068 Peripheral Access Control Register (AIPS0_PACRO) 32 R/W Undefined 19.2.3/396
4000_006C Peripheral Access Control Register (AIPS0_PACRP) 32 R/W Undefined 19.2.3/396
4008_0000 Master Privilege Register A (AIPS1_MPRA) 32 R/W Undefined 19.2.1/387
4008_0020 Peripheral Access Control Register (AIPS1_PACRA) 32 R/W 4444_4444h 19.2.2/391
4008_0024 Peripheral Access Control Register (AIPS1_PACRB) 32 R/W 4444_4444h 19.2.2/391
4008_0028 Peripheral Access Control Register (AIPS1_PACRC) 32 R/W 4444_4444h 19.2.2/391
4008_002C Peripheral Access Control Register (AIPS1_PACRD) 32 R/W 4444_4444h 19.2.2/391
4008_0040 Peripheral Access Control Register (AIPS1_PACRE) 32 R/W Undefined 19.2.3/396
4008_0044 Peripheral Access Control Register (AIPS1_PACRF) 32 R/W Undefined 19.2.3/396
4008_0048 Peripheral Access Control Register (AIPS1_PACRG) 32 R/W Undefined 19.2.3/396
4008_004C Peripheral Access Control Register (AIPS1_PACRH) 32 R/W Undefined 19.2.3/396
4008_0050 Peripheral Access Control Register (AIPS1_PACRI) 32 R/W Undefined 19.2.3/396
4008_0054 Peripheral Access Control Register (AIPS1_PACRJ) 32 R/W Undefined 19.2.3/396
4008_0058 Peripheral Access Control Register (AIPS1_PACRK) 32 R/W Undefined 19.2.3/396
4008_005C Peripheral Access Control Register (AIPS1_PACRL) 32 R/W Undefined 19.2.3/396
4008_0060 Peripheral Access Control Register (AIPS1_PACRM) 32 R/W Undefined 19.2.3/396
4008_0064 Peripheral Access Control Register (AIPS1_PACRN) 32 R/W Undefined 19.2.3/396
4008_0068 Peripheral Access Control Register (AIPS1_PACRO) 32 R/W Undefined 19.2.3/396
4008_006C Peripheral Access Control Register (AIPS1_PACRP) 32 R/W Undefined 19.2.3/396
19.2.1 Master Privilege Register A (AIPSx_MPRA)
The MPRA register specifies identical 4-bit fields defining the access-privilege level
associated with a bus master in the device to the various peripherals. The register
provides one field per bus master.
Chapter 19 Peripheral Bridge (AIPS-Lite)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 387