Information

Section Number Title Page
46.2.5 SIN — Serial Input......................................................................................................................................1209
46.2.6 SOUT — Serial Output................................................................................................................................1209
46.2.7 SCK — Serial Clock....................................................................................................................................1209
46.3 Memory Map/Register Definition.................................................................................................................................1210
46.3.1 DSPI Module Configuration Register (SPIx_MCR)....................................................................................1212
46.3.2 DSPI Transfer Count Register (SPIx_TCR)................................................................................................1215
46.3.3 DSPI Clock and Transfer Attributes Register (In Master Mode) (SPIx_CTARn)......................................1215
46.3.4 DSPI Clock and Transfer Attributes Register (In Slave Mode) (SPIx_CTARn_SLAVE)..........................1220
46.3.5 DSPI Status Register (SPIx_SR)..................................................................................................................1221
46.3.6 DSPI DMA/Interrupt Request Select and Enable Register (SPIx_RSER)..................................................1224
46.3.7 DSPI PUSH TX FIFO Register In Master Mode (SPIx_PUSHR)...............................................................1226
46.3.8 DSPI PUSH TX FIFO Register In Slave Mode (SPIx_PUSHR_SLAVE)..................................................1227
46.3.9 DSPI POP RX FIFO Register (SPIx_POPR)...............................................................................................1228
46.3.10 DSPI Transmit FIFO Registers (SPIx_TXFRn)...........................................................................................1229
46.3.11 DSPI Receive FIFO Registers (SPIx_RXFRn)............................................................................................1230
46.4 Functional Description..................................................................................................................................................1230
46.4.1 Start and Stop of DSPI Transfers.................................................................................................................1231
46.4.2 Serial Peripheral Interface (SPI) Configuration...........................................................................................1232
46.4.3 DSPI Baud Rate and Clock Delay Generation.............................................................................................1236
46.4.4 Transfer Formats..........................................................................................................................................1239
46.4.5 Continuous Serial Communications Clock..................................................................................................1244
46.4.6 Slave Mode Operation Constraints..............................................................................................................1246
46.4.7 Interrupts/DMA Requests............................................................................................................................1247
46.4.8 Power Saving Features.................................................................................................................................1249
46.5 Initialization/Application Information..........................................................................................................................1250
46.5.1 How to Manage DSPI Queues.....................................................................................................................1250
46.5.2 Switching Master and Slave Mode..............................................................................................................1251
46.5.3 Baud Rate Settings.......................................................................................................................................1251
46.5.4 Delay Settings..............................................................................................................................................1252
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
42 Freescale Semiconductor, Inc.