Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_90FC TCD Control and Status (DMA_TCD7_CSR) 16 R/W Undefined
21.3.29/
466
4000_90FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD7_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
468
4000_90FE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD7_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
469
4000_9100 TCD Source Address (DMA_TCD8_SADDR) 32 R/W Undefined
21.3.17/
457
4000_9104 TCD Signed Source Address Offset (DMA_TCD8_SOFF) 16 R/W Undefined
21.3.18/
458
4000_9106 TCD Transfer Attributes (DMA_TCD8_ATTR) 16 R/W Undefined
21.3.19/
458
4000_9108
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD8_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
459
4000_9108
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD8_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
460
4000_9108
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD8_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
461
4000_910C
TCD Last Source Address Adjustment
(DMA_TCD8_SLAST)
32 R/W Undefined
21.3.23/
462
4000_9110 TCD Destination Address (DMA_TCD8_DADDR) 32 R/W Undefined
21.3.24/
462
4000_9114
TCD Signed Destination Address Offset
(DMA_TCD8_DOFF)
16 R/W Undefined
21.3.25/
463
4000_9116
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD8_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
463
4000_9116 DMA_TCD8_CITER_ELINKNO 16 R/W Undefined
21.3.27/
464
4000_9118
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD8_DLASTSGA)
32 R/W Undefined
21.3.28/
465
4000_911C TCD Control and Status (DMA_TCD8_CSR) 16 R/W Undefined
21.3.29/
466
4000_911E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD8_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
468
4000_911E
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD8_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
469
4000_9120 TCD Source Address (DMA_TCD9_SADDR) 32 R/W Undefined
21.3.17/
457
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
428 Freescale Semiconductor, Inc.