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ManualsBrandsNXP SEMICONDUCTORS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 80 (12x12) 32-Bit 100 MHz I/O number 52

Section Number Title Page

46.5.5 Calculation of FIFO Pointer Addresses.......................................................................................................1253

Chapter 47

Inter-Integrated Circuit (I2C)

47.1 Introduction...................................................................................................................................................................1257

47.1.1 Features........................................................................................................................................................1257

47.1.2 Modes of Operation.....................................................................................................................................1258

47.1.3 Block Diagram.............................................................................................................................................1258

47.2 I2C Signal Descriptions................................................................................................................................................1259

47.3 Memory Map and Register Descriptions......................................................................................................................1259

47.3.1 I2C Address Register 1 (I2Cx_A1)..............................................................................................................1261

47.3.2 I2C Frequency Divider register (I2Cx_F)....................................................................................................1261

47.3.3 I2C Control Register 1 (I2Cx_C1)...............................................................................................................1262

47.3.4 I2C Status Register (I2Cx_S).......................................................................................................................1264

47.3.5 I2C Data I/O register (I2Cx_D)...................................................................................................................1266

47.3.6 I2C Control Register 2 (I2Cx_C2)...............................................................................................................1267

47.3.7 I2C Programmable Input Glitch Filter register (I2Cx_FLT).......................................................................1268

47.3.8 I2C Range Address register (I2Cx_RA)......................................................................................................1268

47.3.9 I2C SMBus Control and Status register (I2Cx_SMB).................................................................................1269

47.3.10 I2C Address Register 2 (I2Cx_A2)..............................................................................................................1270

47.3.11 I2C SCL Low Timeout Register High (I2Cx_SLTH)..................................................................................1271

47.3.12 I2C SCL Low Timeout Register Low (I2Cx_SLTL)...................................................................................1271

47.4 Functional Description..................................................................................................................................................1272

47.4.1 I2C Protocol.................................................................................................................................................1272

47.4.2 10-bit Address..............................................................................................................................................1277

47.4.3 Address Matching........................................................................................................................................1278

47.4.4 System Management Bus Specification.......................................................................................................1279

47.4.5 Resets...........................................................................................................................................................1282

47.4.6 Interrupts......................................................................................................................................................1282

47.4.7 Programmable Input Glitch Filter................................................................................................................1284

K20 Sub-Family Reference Manual, Rev. 6, Nov 2011

Freescale Semiconductor, Inc. 43