Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_91A0 TCD Source Address (DMA_TCD13_SADDR) 32 R/W Undefined
21.3.17/
457
4000_91A4 TCD Signed Source Address Offset (DMA_TCD13_SOFF) 16 R/W Undefined
21.3.18/
458
4000_91A6 TCD Transfer Attributes (DMA_TCD13_ATTR) 16 R/W Undefined
21.3.19/
458
4000_91A8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD13_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
459
4000_91A8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD13_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
460
4000_91A8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD13_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
461
4000_91AC
TCD Last Source Address Adjustment
(DMA_TCD13_SLAST)
32 R/W Undefined
21.3.23/
462
4000_91B0 TCD Destination Address (DMA_TCD13_DADDR) 32 R/W Undefined
21.3.24/
462
4000_91B4
TCD Signed Destination Address Offset
(DMA_TCD13_DOFF)
16 R/W Undefined
21.3.25/
463
4000_91B6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD13_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
463
4000_91B6 DMA_TCD13_CITER_ELINKNO 16 R/W Undefined
21.3.27/
464
4000_91B8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD13_DLASTSGA)
32 R/W Undefined
21.3.28/
465
4000_91BC TCD Control and Status (DMA_TCD13_CSR) 16 R/W Undefined
21.3.29/
466
4000_91BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD13_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
468
4000_91BE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD13_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
469
4000_91C0 TCD Source Address (DMA_TCD14_SADDR) 32 R/W Undefined
21.3.17/
457
4000_91C4 TCD Signed Source Address Offset (DMA_TCD14_SOFF) 16 R/W Undefined
21.3.18/
458
4000_91C6 TCD Transfer Attributes (DMA_TCD14_ATTR) 16 R/W Undefined
21.3.19/
458
4000_91C8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD14_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
459
4000_91C8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD14_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
460
Table continues on the next page...
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
432 Freescale Semiconductor, Inc.