Information

DMA memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4000_91C8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD14_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
461
4000_91CC
TCD Last Source Address Adjustment
(DMA_TCD14_SLAST)
32 R/W Undefined
21.3.23/
462
4000_91D0 TCD Destination Address (DMA_TCD14_DADDR) 32 R/W Undefined
21.3.24/
462
4000_91D4
TCD Signed Destination Address Offset
(DMA_TCD14_DOFF)
16 R/W Undefined
21.3.25/
463
4000_91D6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD14_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
463
4000_91D6 DMA_TCD14_CITER_ELINKNO 16 R/W Undefined
21.3.27/
464
4000_91D8
TCD Last Destination Address Adjustment/Scatter Gather
Address (DMA_TCD14_DLASTSGA)
32 R/W Undefined
21.3.28/
465
4000_91DC TCD Control and Status (DMA_TCD14_CSR) 16 R/W Undefined
21.3.29/
466
4000_91DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Enabled)
(DMA_TCD14_BITER_ELINKYES)
16 R/W Undefined
21.3.30/
468
4000_91DE
TCD Beginning Minor Loop Link, Major Loop Count
(Channel Linking Disabled)
(DMA_TCD14_BITER_ELINKNO)
16 R/W Undefined
21.3.31/
469
4000_91E0 TCD Source Address (DMA_TCD15_SADDR) 32 R/W Undefined
21.3.17/
457
4000_91E4 TCD Signed Source Address Offset (DMA_TCD15_SOFF) 16 R/W Undefined
21.3.18/
458
4000_91E6 TCD Transfer Attributes (DMA_TCD15_ATTR) 16 R/W Undefined
21.3.19/
458
4000_91E8
TCD Minor Byte Count (Minor Loop Disabled)
(DMA_TCD15_NBYTES_MLNO)
32 R/W Undefined
21.3.20/
459
4000_91E8
TCD Signed Minor Loop Offset (Minor Loop Enabled and
Offset Disabled) (DMA_TCD15_NBYTES_MLOFFNO)
32 R/W Undefined
21.3.21/
460
4000_91E8
TCD Signed Minor Loop Offset (Minor Loop and Offset
Enabled) (DMA_TCD15_NBYTES_MLOFFYES)
32 R/W Undefined
21.3.22/
461
4000_91EC
TCD Last Source Address Adjustment
(DMA_TCD15_SLAST)
32 R/W Undefined
21.3.23/
462
4000_91F0 TCD Destination Address (DMA_TCD15_DADDR) 32 R/W Undefined
21.3.24/
462
4000_91F4
TCD Signed Destination Address Offset
(DMA_TCD15_DOFF)
16 R/W Undefined
21.3.25/
463
4000_91F6
TCD Current Minor Loop Link, Major Loop Count (Channel
Linking Enabled) (DMA_TCD15_CITER_ELINKYES)
16 R/W Undefined
21.3.26/
463
Table continues on the next page...
Chapter 21 Direct Memory Access Controller (eDMA)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 433