Information

DMA_ERR field descriptions (continued)
Field Description
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
3
ERR3
Error In Channel 3
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
2
ERR2
Error In Channel 2
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
1
ERR1
Error In Channel 1
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
0
ERR0
Error In Channel 0
0 An error in the corresponding channel has not occurred
1 An error in the corresponding channel has occurred
21.3.15 Hardware Request Status Register (DMA_HRS)
The HRS provides a bit map for the DMA channels, signaling the presence of a hardware
request for each channel. The hardware request status bits reflect the current state of the
register and qualified (via the ERQ fields) DMA request signals as seen by the DMA’s
arbitration logic. This view into the hardware request signals may be used for debug
purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Address: DMA_HRS is 4000_8000h base + 34h offset = 4000_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
HRS15 HRS14 HRS13 HRS12 HRS11 HRS10
HRS9 HRS8 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Memory map/register definition
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
454 Freescale Semiconductor, Inc.