Information

Section Number Title Page
48.8.2 ISO-7816 initialization sequence.................................................................................................................1369
48.8.3 Initialization sequence (non ISO-7816).......................................................................................................1371
48.8.4 Overrun (OR) flag implications...................................................................................................................1372
48.8.5 Overrun NACK considerations....................................................................................................................1373
48.8.6 Match address registers................................................................................................................................1374
48.8.7 Modem feature.............................................................................................................................................1374
48.8.8 IrDA minimum pulse width.........................................................................................................................1375
48.8.9 Clearing 7816 wait timer (WT, BWT, CWT) interrupts..............................................................................1375
48.8.10 Legacy and reverse compatibility considerations........................................................................................1376
Chapter 49
Secured digital host controller (SDHC)
49.1 Introduction...................................................................................................................................................................1377
49.2 Overview.......................................................................................................................................................................1377
49.2.1 Supported types of cards..............................................................................................................................1377
49.2.2 SDHC block diagram...................................................................................................................................1378
49.2.3 Features........................................................................................................................................................1379
49.2.4 Modes and operations..................................................................................................................................1380
49.3 SDHC signal descriptions.............................................................................................................................................1381
49.4 Memory map and register definition.............................................................................................................................1382
49.4.1 DMA System Address Register (SDHC_DSADDR)..................................................................................1383
49.4.2 Block Attributes Register (SDHC_BLKATTR)..........................................................................................1384
49.4.3 Command Argument Register (SDHC_CMDARG)....................................................................................1385
49.4.4 Transfer Type Register (SDHC_XFERTYP)..............................................................................................1386
49.4.5 Command Response 0 (SDHC_CMDRSP0)...............................................................................................1390
49.4.6 Command Response 1 (SDHC_CMDRSP1)...............................................................................................1391
49.4.7 Command Response 2 (SDHC_CMDRSP2)...............................................................................................1391
49.4.8 Command Response 3 (SDHC_CMDRSP3)...............................................................................................1391
49.4.9 Buffer Data Port Register (SDHC_DATPORT)..........................................................................................1393
49.4.10 Present State Register (SDHC_PRSSTAT).................................................................................................1393
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
46 Freescale Semiconductor, Inc.