Information

Section Number Title Page
49.4.11 Protocol Control Register (SDHC_PROCTL).............................................................................................1398
49.4.12 System Control Register (SDHC_SYSCTL)...............................................................................................1402
49.4.13 Interrupt Status Register (SDHC_IRQSTAT).............................................................................................1405
49.4.14 Interrupt Status Enable Register (SDHC_IRQSTATEN)............................................................................1411
49.4.15 Interrupt Signal Enable Register (SDHC_IRQSIGEN)...............................................................................1414
49.4.16 Auto CMD12 Error Status Register (SDHC_AC12ERR)...........................................................................1416
49.4.17 Host Controller Capabilities (SDHC_HTCAPBLT)....................................................................................1419
49.4.18 Watermark Level Register (SDHC_WML).................................................................................................1421
49.4.19 Force Event Register (SDHC_FEVT)..........................................................................................................1421
49.4.20 ADMA Error Status Register (SDHC_ADMAES)......................................................................................1424
49.4.21 ADMA System Address Register (SDHC_ADSADDR).............................................................................1426
49.4.22 Vendor Specific Register (SDHC_VENDOR)............................................................................................1426
49.4.23 MMC Boot Register (SDHC_MMCBOOT)................................................................................................1428
49.4.24 Host Controller Version (SDHC_HOSTVER)............................................................................................1429
49.5 Functional description...................................................................................................................................................1430
49.5.1 Data buffer...................................................................................................................................................1430
49.5.2 DMA crossbar switch interface....................................................................................................................1436
49.5.3 SD protocol unit...........................................................................................................................................1442
49.5.4 Clock & reset manager.................................................................................................................................1444
49.5.5 Clock generator............................................................................................................................................1445
49.5.6 SDIO card interrupt......................................................................................................................................1445
49.5.7 Card insertion and removal detection..........................................................................................................1447
49.5.8 Power management and wakeup events.......................................................................................................1448
49.5.9 MMC fast boot.............................................................................................................................................1449
49.6 Initialization/application of SDHC...............................................................................................................................1451
49.6.1 Command send and response receive basic operation.................................................................................1451
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 47