Information

Section Number Title Page
49.6.2 Card identification mode..............................................................................................................................1452
49.6.3 Card access...................................................................................................................................................1457
49.6.4 Switch function............................................................................................................................................1468
49.6.5 ADMA operation.........................................................................................................................................1470
49.6.6 Fast boot operation.......................................................................................................................................1471
49.6.7 Commands for MMC/SD/SDIO/CE-ATA...................................................................................................1475
49.7 Software restrictions.....................................................................................................................................................1481
49.7.1 Initialization active.......................................................................................................................................1481
49.7.2 Software polling procedure..........................................................................................................................1482
49.7.3 Suspend operation........................................................................................................................................1482
49.7.4 Data length setting.......................................................................................................................................1482
49.7.5 (A)DMA address setting..............................................................................................................................1482
49.7.6 Data port access...........................................................................................................................................1483
49.7.7 Change clock frequency...............................................................................................................................1483
49.7.8 Multi-block read...........................................................................................................................................1483
Chapter 50
Integrated interchip sound (I2S)
50.1 Introduction...................................................................................................................................................................1485
50.1.1 Block diagram..............................................................................................................................................1485
50.1.2 Features........................................................................................................................................................1486
50.1.3 Modes of operation......................................................................................................................................1487
50.2 I2S signal descriptions..................................................................................................................................................1489
50.3 Memory map/register definition...................................................................................................................................1493
50.3.1 I
2
S Transmit Data Registers 0 (I2Sx_TX0).................................................................................................1495
50.3.2 I
2
S Transmit Data Registers 1 (I2Sx_TX1).................................................................................................1495
50.3.3 I
2
S Receive Data Registers 0 (I2Sx_RX0)...................................................................................................1496
50.3.4 I
2
S Receive Data Registers 1 (I2Sx_RX1)...................................................................................................1496
50.3.5 I
2
S Control Register (I2Sx_CR)...................................................................................................................1497
50.3.6 I
2
S Interrupt Status Register (I2Sx_ISR).....................................................................................................1500
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
48 Freescale Semiconductor, Inc.