Information

Section Number Title Page
50.3.7 I
2
S Interrupt Enable Register (I2Sx_IER)....................................................................................................1505
50.3.8 I
2
S Transmit Configuration Register (I2Sx_TCR).......................................................................................1509
50.3.9 I
2
S Receive Configuration Register (I2Sx_RCR)........................................................................................1511
50.3.10 I
2
S Transmit Clock Control Registers (I2Sx_TCCR)..................................................................................1513
50.3.11 I
2
S Receive Clock Control Registers (I2Sx_RCCR)...................................................................................1515
50.3.12 I
2
S FIFO Control/Status Register (I2Sx_FCSR)..........................................................................................1516
50.3.13 I
2
S AC97 Control Register (I2Sx_ACNT)...................................................................................................1522
50.3.14 I
2
S AC97 Command Address Register (I2Sx_ACADD).............................................................................1523
50.3.15 I
2
S AC97 Command Data Register (I2Sx_ACDAT)...................................................................................1524
50.3.16 I
2
S AC97 Tag Register (I2Sx_ATAG)........................................................................................................1524
50.3.17 I
2
S Transmit Time Slot Mask Register (I2Sx_TMSK)................................................................................1525
50.3.18 I
2
S Receive Time Slot Mask Register (I2Sx_RMSK).................................................................................1525
50.3.19 I
2
S AC97 Channel Status Register (I2Sx_ACCST).....................................................................................1526
50.3.20 I
2
S AC97 Channel Enable Register (I2Sx_ACCEN)...................................................................................1526
50.3.21 I
2
S AC97 Channel Disable Register (I2Sx_ACCDIS).................................................................................1527
50.4 Functional description...................................................................................................................................................1527
50.4.1 Detailed operating mode descriptions..........................................................................................................1527
50.4.2 I2S clocking.................................................................................................................................................1543
50.4.3 External frame and clock operation.............................................................................................................1548
50.4.4 Receive interrupt enable bit description.......................................................................................................1550
50.4.5 Transmit interrupt enable bit description.....................................................................................................1551
50.4.6 Internal frame and clock shutdown..............................................................................................................1552
50.4.7 Reset.............................................................................................................................................................1553
50.5 Initialization/application information...........................................................................................................................1553
Chapter 51
General purpose input/output (GPIO)
51.1 Introduction...................................................................................................................................................................1557
51.1.1 Features........................................................................................................................................................1557
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 49