Information

Section Number Title Page
53.4 Functional description...................................................................................................................................................1603
53.4.1 JTAGC reset configuration..........................................................................................................................1603
53.4.2 IEEE 1149.1-2001 (JTAG) Test Access Port..............................................................................................1603
53.4.3 TAP controller state machine.......................................................................................................................1603
53.4.4 JTAGC block instructions............................................................................................................................1605
53.4.5 Boundary scan..............................................................................................................................................1608
53.5 Initialization/Application information..........................................................................................................................1608
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
52 Freescale Semiconductor, Inc.