Information

MCG_C1 field descriptions (continued)
Field Description
0 Internal reference clock is disabled in Stop mode.
1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI
modes before entering Stop mode.
24.3.2 MCG Control 2 Register (MCG_C2)
Address: MCG_C2 is 4006_4000h base + 1h offset = 4006_4001h
Bit 7 6 5 4 3 2 1 0
Read 0 0
RANGE
HGO EREFS
LP IRCS
Write
Reset
0 0 0 0 0 0 0 0
MCG_C2 field descriptions
Field Description
7
Reserved
This read-only field is reserved and always has the value zero.
6
Reserved
This read-only field is reserved and always has the value zero.
5–4
RANGE
Frequency Range Select
Selects the frequency range for the crystal oscillator or external clock source. Refer to the Oscillator
(OSC) chapter for more details and the device data sheet for the frequency ranges used.
00 Encoding 0 — Low frequency range selected for the crystal oscillator .
01 Encoding 1 — High frequency range selected for the crystal oscillator .
1X Encoding 2 — Very high frequency range selected for the crystal oscillator .
3
HGO
High Gain Oscillator Select
Controls the crystal oscillator mode of operation. Refer to the Oscillator (OSC) chapter for more details.
0 Configure crystal oscillator for low-power operation.
1 Configure crystal oscillator for high-gain operation.
2
EREFS
External Reference Select
Selects the source for the external reference clock. Refer to the Oscillator (OSC) chapter for more details.
0 External reference clock requested.
1 Oscillator requested.
1
LP
Low Power Select
Controls whether the FLL (or PLL) is disabled in BLPI and BLPE modes. In FBE or PBE modes, setting
this bit to 1 will transition the MCG into BLPE mode; in FBI mode, setting this bit to 1 will transition the
MCG into BLPI mode. In any other MCG mode, LP bit has no affect.
Table continues on the next page...
Chapter 24 Multipurpose Clock Generator (MCG)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 529