Information

MCG_C6 field descriptions (continued)
Field Description
Table 24-9. PLL VCO Divide Factor (continued)
00001 25 01001 33 10001 41 11001 49
00010 26 01010 34 10010 42 11010 50
00011 27 01011 35 10011 43 11011 51
00100 28 01100 36 10100 44 11100 52
00101 29 01101 37 10101 45 11101 53
00110 30 01110 38 10110 46 11110 54
00111 31 01111 39 10111 47 11111 55
24.3.7 MCG Status Register (MCG_S)
Address: MCG_S is 4006_4000h base + 6h offset = 4006_4006h
Bit 7 6 5 4 3 2 1 0
Read
LOLS LOCK
PLLST IREFST CLKST
OSCINIT
IRCST
Write
Reset
0 0 0 1 0 0 0 0
MCG_S field descriptions
Field Description
7
LOLS
Loss of Lock Status
This bit is a sticky bit indicating the lock status for the PLL. LOLS is set if after acquiring lock, the PLL
output frequency has fallen outside the lock exit frequency tolerance, D
unl
. LOLIE determines whether an
interrupt request is made when LOLS is set. LOLRE determines whether a reset request is made when
LOLS0 is set. This bit is cleared by reset or by writing a logic 1 to it when set. Writing a logic 0 to this bit
has no effect.
0 PLL has not lost lock since LOLS was last cleared.
1 PLL has lost lock since LOLS was last cleared.
6
LOCK
Lock Status
This bit indicates whether the PLL has acquired lock. Lock detection is disabled when not operating in
either PBE or PEE mode unless PLLCLKEN =1 and the MCG is not configured in BLPI or BLPE mode.
Table continues on the next page...
Chapter 24 Multipurpose Clock Generator (MCG)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 535