Information

• Interface between the device and the dual-bank flash memory:
• 8-bit, 16-bit, and 32-bit read operations to program flash memory.
• For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory
return the second read data with no wait states. The memory returns 64 bits via
the 32-bit bus access.
• Crossbar master access protection for setting no access, read only access, write
only access, or read/write access for each crossbar master.
• For bank 0 and bank 1: Acceleration of data transfer from program flash memory to
the device:
• 64-bit prefetch speculation buffer with controls for instruction/data access per
master and bank
• 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with
controls for replacement algorithm and lock per way for each bank
• Single-entry buffer with enable per bank
• Invalidation control for the speculation buffer and the single-entry buffer
27.2 Modes of operation
The FMC only operates when the device accesses the flash memory.
In terms of device power modes, the FMC only operates in run and wait modes, including
VLPR and VLPW modes.
For any device power mode where the flash memory cannot be accessed, the FMC is
disabled.
27.3 External signal description
The FMC has no external signals.
Memory map and register descriptions
The programming model consists of the FMC control registers and the program visible
cache (data and tag/valid entries).
27.4
Modes of operation
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
576 Freescale Semiconductor, Inc.