Information

Table 2-3. System modules (continued)
Module Description
Low-leakage wakeup unit (LLWU) The LLWU module allows the device to wake from low leakage power modes (LLS
and VLLS) through various internal peripheral and external pin sources.
Miscellaneous control module (MCM) The MCM includes integration logic and embedded trace buffer details.
Crossbar switch (XBS) The XBS connects bus masters and bus slaves, allowing all bus masters to
access different bus slaves simultaneously and providing arbitration among the
bus masters when they access the same slave.
Memory protection unit (MPU) The MPU provides memory protection and task isolation. It concurrently monitors
all bus master transactions for the slave connections.
Peripheral bridges The peripheral bridge converts the crossbar switch interface to an interface to
access a majority of peripherals on the device.
DMA multiplexer (DMAMUX) The DMA multiplexer selects from many DMA requests down to 16 for the DMA
controller.
Direct memory access (DMA) controller The DMA controller provides programmable channels with transfer control
descriptors for data movement via dual-address transfers for 8-, 16-, 32- and 128-
bit data values.
External watchdog monitor (EWM) The EWM is a redundant mechanism to the software watchdog module that
monitors both internal and external system operation for fail conditions.
Software watchdog (WDOG) The WDOG monitors internal system operation and forces a reset in case of
failure. It can run from an independent 1 KHz low power oscillator with a
programmable refresh window to detect deviations in program flow or system
frequency.
2.3.3 Memories and Memory Interfaces
The following memories and memory interfaces are available on this device.
Table 2-4. Memories and memory interfaces
Module Description
Flash memory • Program flash memory — non-volatile flash memory that can execute
program code
• FlexMemory — encompasses the following memory types:
• Programming acceleration RAM — RAM memory that accelerates
flash programming
Flash memory controller Manages the interface between the device and the on-chip flash memory.
SRAM Internal system RAM. Partial SRAM kept powered in VLLS2 low leakage mode.
SRAM controller Manages simultaneous accesses to system RAM by multiple master peripherals
and core.
System register file 32-byte register file that is accessible during all power modes and is powered by
VDD.
VBAT register file 32-byte register file that is accessible during all power modes and is powered by
VBAT.
Table continues on the next page...
Module Functional Categories
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
58 Freescale Semiconductor, Inc.