Information

FMC_PFAPR field descriptions (continued)
Field Description
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
19
M3PFD
Master 3 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
18
M2PFD
Master 2 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
17
M1PFD
Master 1 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
16
M0PFD
Master 0 Prefetch Disable
These bits control whether prefetching is enabled based on the logical number of the requesting crossbar
switch master. This field is further qualified by the PFBnCR[BxDPE,BxIPE] bits.
0 Prefetching for this master is enabled.
1 Prefetching for this master is disabled.
15–14
M7AP[1:0]
Master 7 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master.
01 Only read accesses may be performed by this master.
10 Only write accesses may be performed by this master.
11 Both read and write accesses may be performed by this master.
13–12
M6AP[1:0]
Master 6 Access Protection
This field controls whether read and write access to the flash are allowed based on the logical master
number of the requesting crossbar switch master.
00 No access may be performed by this master
01 Only read accesses may be performed by this master
10 Only write accesses may be performed by this master
11 Both read and write accesses may be performed by this master
11–10
M5AP[1:0]
Master 5 Access Protection
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
584 Freescale Semiconductor, Inc.