Information

FMC_PFB0CR field descriptions (continued)
Field Description
2
B0DPE
Bank 0 Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0 Do not prefetch in response to data references.
1 Enable prefetches in response to data references.
1
B0IPE
Bank 0 Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0 Do not prefetch in response to instruction fetches.
1 Enable prefetches in response to instruction fetches.
0
B0SEBE
Bank 0 Single Entry Buffer Enable
This bit controls whether the single entry page buffer is enabled in response to flash read accesses. Its
operation is independent from bank 1's cache.
A high-to-low transition of this enable forces the page buffer to be invalidated.
0 Single entry buffer is disabled.
1 Single entry buffer is enabled.
27.4.3 Flash Bank 1 Control Register (FMC_PFB1CR)
This register has a format similar to that for PFB0CR, except it controls the operation of
flash bank 1, and the "global" cache control fields are empty.
Address: FMC_PFB1CR is 4001_F000h base + 8h offset = 4001_F008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
B1RWSC[3:0] 0
B1MW[1:0]
0
W
Reset
0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
B1DCE
B1ICE
B1DPE
B1IPE
B1SEBE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1
FMC_PFB1CR field descriptions
Field Description
31–28
B1RWSC[3:0]
Bank 1 Read Wait State Control
Table continues on the next page...
Memory map and register descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
588 Freescale Semiconductor, Inc.