Information

FMC_PFB1CR field descriptions (continued)
Field Description
This read-only field defines the number of wait states required to access the bank 1 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
27–19
Reserved
This read-only field is reserved and always has the value zero.
18–17
B1MW[1:0]
Bank 1 Memory Width
This read-only field defines the width of the bank 1 memory.
00 32 bits
01 64 bits
10 Reserved
11 Reserved
16
Reserved
This read-only field is reserved and always has the value zero.
15–8
Reserved
This read-only field is reserved and always has the value zero.
7–5
Reserved
This read-only field is reserved and always has the value zero.
4
B1DCE
Bank 1 Data Cache Enable
This bit controls whether data references are loaded into the cache.
0 Do not cache data references.
1 Cache data references.
3
B1ICE
Bank 1 Instruction Cache Enable
This bit controls whether instruction fetches are loaded into the cache.
0 Do not cache instruction fetches.
1 Cache instruction fetches.
2
B1DPE
Bank 1 Data Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to data references.
0 Do not prefetch in response to data references.
1 Enable prefetches in response to data references.
1
B1IPE
Bank 1 Instruction Prefetch Enable
This bit controls whether prefetches (or speculative accesses) are initiated in response to instruction
fetches.
0 Do not prefetch in response to instruction fetches.
1 Enable prefetches in response to instruction fetches.
Table continues on the next page...
Chapter 27 Flash Memory Controller (FMC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 589