Information

FTFL_FCNFG field descriptions (continued)
Field Description
This bit issues a request to the memory controller to execute the Erase All Blocks command and release
security. ERSAREQ is not directly writable but is under indirect user control. Refer to the device's Chip
Configuration details on how to request this command.
The ERSAREQ bit sets when an erase all request is triggered external to the FTFL and CCIF is set (no
command is currently being executed). ERSAREQ is cleared by the FTFL when the operation completes.
0 No request or request complete
1 Request to:
1. run the Erase All Blocks command,
2. verify the erased state,
3. program the security byte in the Flash Configuration Field to the unsecure state, and
4. release MCU security by setting the FSEC[SEC] field to the unsecure state.
4
ERSSUSP
Erase Suspend
The ERSSUSP bit allows the user to suspend (interrupt) the Erase Flash Sector command while it is
executing.
0 No suspend requested
1 Suspend the current Erase Flash Sector command execution.
3
SWAP
Swap
For program flash only configurations, the SWAP flag indicates which physical program flash block is
located at relative address 0x0000. The state of the SWAP flag is set by the FTFL during the reset
sequence . See the Swap Control command section for information on swap management.
0 Physical program flash 0 is located at relative address 0x0000
1 If the PFLSH flag is set, physical program flash 1 is located at relative address 0x0000. If the PFLSH
flag is not set, physical program flash 0 is located at relative address 0x0000
2
PFLSH
FTFL configuration
0 Reserved
1 FTFL configured for program flash only, without support for data flash and/or EEPROM
1
RAMRDY
RAM Ready
This flag indicates the current status of the programming acceleration RAM .
This bit should always be set.
0 Programming acceleration RAM is not available.
1 Programming acceleration RAM is available.
0
EEERDY
This field is reserved.
0
1
28.33.3 Flash Security Register (FTFL_FSEC)
This read-only register holds all bits associated with the security of the MCU and FTFL
module.
Memory Map and Registers
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
612 Freescale Semiconductor, Inc.