Information

28.4.10 FTFL Command Description
This section describes all FTFL commands that can be launched by a command write
sequence. The FTFL sets the FSTAT[ACCERR] bit and aborts the command execution if
any of the following illegal conditions occur:
• There is an unrecognized command code in the FCCOB FCMD field.
• There is an error in a FCCOB field for the specific commands. Refer to the error
handling table provided for each command.
Ensure that the ACCERR and FPVIOL bits in the FSTAT register are cleared prior to
starting the command write sequence. As described in Launch the Command by Clearing
CCIF, a new command cannot be launched while these error flags are set.
Do not attempt to read a flash block while the FTFL is running a command (CCIF = 0)
on that same block. The FTFL may return invalid data to the MCU with the collision
error flag (FSTAT[RDCOLERR]) set.
When required by the command, address bit 23 selects between:
• program flash 0 (=0) block
• program flash 1 (=1) block
CAUTION
Flash data must be in the erased state before being
programmed. Cumulative programming of bits (adding more
zeros) is not allowed.
28.4.10.1 Read 1s Block Command
The Read 1s Block command checks to see if an entire program flash block has been
erased to the specified margin level. The FCCOB flash address bits determine which
logical block is erase-verified.
Table 28-27. Read 1s Block Command FCCOB Requirements
FCCOB Number FCCOB Contents [7:0]
0 0x00 (RD1BLK)
1 Flash address [23:16] in the flash block to be verified
2 Flash address [15:8] in the flash block to be verified
Table continues on the next page...
Flash Operation in Low-Power Modes
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
626 Freescale Semiconductor, Inc.