Information

Chapter 29
External Bus Interface (FlexBus)
29.1 Introduction
NOTE
For the chip-specific implementation details of this module's
instances see the chip configuration chapter.
This chapter describes external bus data transfer operations and error conditions. It
describes transfers initiated by the core processor (or any other bus master) and includes
detailed timing diagrams showing the interaction of signals in supported bus operations.
29.1.1 Overview
A multi-function external bus interface called the FlexBus interface controller is provided
on the device with basic functionality of interfacing to slave-only devices. It can be
directly connected to the following asynchronous or synchronous devices with little or no
additional circuitry:
• External ROMs
• Flash memories
• Programmable logic devices
• Other simple target (slave) devices
For asynchronous devices, a simple chip-select based interface can be used.
The FlexBus interface has up to six general purpose chip-selects,
FB_CS[5:0]. The actual
number of chip selects available depends upon the device and its pin configuration.
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 651