Information

29.1.2 Features
Key FlexBus features include:
• Six independent, user-programmable chip-select signals (FB_CS[5:0]) that can
interface with external SRAM, PROM, EPROM, EEPROM, flash, and other
peripherals
• 8-, 16-, and 32-bit port sizes with configuration for multiplexed or non-multiplexed
address and data buses
• 8-bit, 16-bit, 32-bit, and 16-byte transfers
• Programmable burst- and burst-inhibited transfers selectable for each chip select and
transfer direction
• Programmable address-setup time with respect to the assertion of chip select
• Programmable address-hold time with respect to the negation of chip select and
transfer direction
• Extended address latch enable option helps with glueless connections to synchronous
and asynchronous memory devices
29.1.3 Modes of Operation
The external interface is a configurable multiplexed bus set to one of the following
modes:
• Multiplexed 32-bit address and 32-bit data
• Multiplexed 32-bit address and 16-bit data (non-multiplexed 16-bit address and 16-
bit data)
•
Multiplexed 32-bit address and 8-bit data (non-multiplexed 24-bit address and 8-bit
data)
• Non-multiplexed 32-bit address and 32-bit data busses
29.2 Signal Descriptions
This section describes the external signals involved in data-transfer operations.
NOTE
Not all of the following signals may be available on a particular
device. See the Chip Configuration details for information on
which signals are available.
Signal Descriptions
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
652 Freescale Semiconductor, Inc.