Information

29.4.6 FlexBus Timing Examples
Note
The timing diagrams throughout this section use signal names
that may not be included on your particular device. Ignore these
extraneous signals.
Note
Throughout this section:
• FB_D[X] indicates a 32-, 16-, or 8-bit wide data bus
• FB_A[Y] indicates an address bus that can be 32, 24, or 16
bits wide.
29.4.6.1 Basic Read Bus Cycle
During a read cycle, the MCU receives data from memory or a peripheral device. The
following figure shows a read cycle flowchart.
1. Decode address.
3. Assert FB_TA (external termination).
1. Negate FB_TA (external termination).
1. Set FB_R/W to read.
2. Assert FB_CSn.
(auto-acknowledge/internal termination).
2. Sample FB_TA low and latch data.
1. Start next cycle.
System
2. Place address on the external address signals.
2. Drive data on the external data signals.
1. Select the appropriate slave device.
3. Assert transfer start.
1. Negate transfer start.
1. FlexBus asserts internal FB_TA
Microcontroller
Figure 29-26. Read Cycle Flowchart
The read cycle timing diagram is shown in the following figure.
Functional Description
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
670 Freescale Semiconductor, Inc.