Information

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-29. Basic Write-Bus Cycle
29.4.6.3 Bus Cycle Sizing
This section shows timing diagrams for various port size scenarios.
29.4.6.3.1 Bus Cycle Sizing—Byte Transfer, 8-bit Device, No Wait States
The following figure illustrates the basic byte read transfer to an 8-bit device with no wait
states:
•
The address is driven on the full FB_AD[31:8] bus in the first clock.
• The device tristates FB_AD[31:24] on the second clock and continues to drive
address on FB_AD[23:0] throughout the bus cycle.
• The external device returns the read data on FB_AD[31:24] and may tristate the data
line or continue driving the data one clock after
FB_TA is sampled asserted.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 673