Information

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-37. Basic Write-Bus Cycle (No Wait States)
If wait states are used, the S1 state repeats continuously until the the chip-select auto-
acknowledge unit asserts internal transfer acknowledge or the external FB_TA is
recognized as asserted. The following figures show a read and write cycle with one wait
state respectively.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 681