Information

Address
Address Data
TSIZ
AA=1
AA=0
AA=1
AA=0
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BE/BWEn
FB_TA
FB_TSIZ[1:0]
Figure 29-41. Write-Bus Cycle with Two Clock Address Setup (No Wait States)
In addition to address setup, a programmable address hold option for each chip select
exists. Address and attributes can be held one to four clocks after chip-select, byte-
selects, and output-enable negate. The following figures show read and write bus cycles
with two clocks of address hold respectively.
Chapter 29 External Bus Interface (FlexBus)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 685