Information

Section Number Title Page
4.3 Flash Memory Map.......................................................................................................................................................155
4.3.1 Alternate Non-Volatile IRC User Trim Description....................................................................................156
4.4 SRAM memory map.....................................................................................................................................................156
4.5 Peripheral bridge (AIPS-Lite0 and AIPS-Lite1) memory maps...................................................................................157
4.5.1 Peripheral Bridge 0 (AIPS-Lite 0) Memory Map........................................................................................157
4.5.2 Peripheral Bridge 1 (AIPS-Lite 1) Memory Map........................................................................................161
4.6 Private Peripheral Bus (PPB) memory map..................................................................................................................165
Chapter 5
Clock Distribution
5.1 Introduction...................................................................................................................................................................167
5.2 Programming model......................................................................................................................................................167
5.3 High-Level device clocking diagram............................................................................................................................167
5.4 Clock definitions...........................................................................................................................................................168
5.4.1 Device clock summary.................................................................................................................................169
5.5 Internal clocking requirements.....................................................................................................................................171
5.5.1 Clock divider values after reset....................................................................................................................172
5.5.2 VLPR mode clocking...................................................................................................................................172
5.6 Clock Gating.................................................................................................................................................................172
5.7 Module clocks...............................................................................................................................................................173
5.7.1 PMC 1-kHz LPO clock................................................................................................................................174
5.7.2 WDOG clocking..........................................................................................................................................175
5.7.3 Debug trace clock.........................................................................................................................................175
5.7.4 PORT digital filter clocking.........................................................................................................................175
5.7.5 LPTMR clocking..........................................................................................................................................176
5.7.6 USB FS OTG Controller clocking...............................................................................................................176
5.7.7 FlexCAN clocking.......................................................................................................................................177
5.7.8 UART clocking............................................................................................................................................177
5.7.9 SDHC clocking............................................................................................................................................178
5.7.10 I2S clocking.................................................................................................................................................178
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 7