Information

Table 30-2. EzPort Commands (continued)
Command Description Code
Address
Bytes
Data Bytes
Accepted when
secure?
RESET Reset Chip 0xB9 0 0 Yes
WRFCCOB Write FCCOB Registers 0xBA 0 12 Yes
6
FAST_RDFCCOB
Read FCCOB registers at high
speed
0xBB 0 1 - 12
2
No
1. Address must be 32-bit aligned (two LSBs must be zero).
2. One byte of dummy data must be shifted in before valid data is shifted out.
3. Address must be 64-bit aligned (three LSBs must be zero).
4. A section is defined as half the size of the flash sector size. Total number of data bytes programmed must be a multiple of
8.
5. Bulk Erase is accepted when security is set only if the BEDIS status bit is not set.
6. Note that the Flash will be in NVM Special mode, restricting which types of commands can be executed through
WRITE_FCCOB when security is enabled.
30.3.1 Command Descriptions
This section describes the module commands.
30.3.1.1 Write Enable
The Write Enable command (WREN) sets the write enable register bit in the EzPort
status register. The write enable bit must be set for a write command (SP, SE, BE,
WRFCCOB) to be accepted. The write enable register bit clears on reset, on a Write
Disable command, and at the completion of write command. This command should not
be used if a write is already in progress.
30.3.1.2 Write Disable
The Write Disable command (WRDI) clears the write enable register bit in the status
register. This command should not be used if a write is already in progress.
30.3.1.3 Read Status Register
The Read Status Register command (RDSR) returns the contents of the EzPort status
register.
Chapter 30 EzPort
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 703