Information

ADCx_SC1n field descriptions (continued)
Field Description
10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved.
11000 Reserved.
11001 Reserved.
11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor
(differential) is selected as input.
11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap
(differential) is selected as input.
11100 Reserved.
11101 When DIFF=0, V
REFSH
is selected as input; when DIFF=1, -V
REFSH
(differential) is selected as
input. Voltage reference selected is determined by the REFSEL bits in the SC2 register.
11110 When DIFF=0, V
REFSL
is selected as input; when DIFF=1, it is reserved. Voltage reference
selected is determined by the REFSEL bits in the SC2 register.
11111 Module disabled.
32.3.2 ADC configuration register 1 (ADCx_CFG1)
CFG1 register selects the mode of operation, clock source, clock divide, and configure
for low power or long sample time.
Addresses: ADC0_CFG1 is 4003_B000h base + 8h offset = 4003_B008h
ADC1_CFG1 is 400B_B000h base + 8h offset = 400B_B008h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
ADLPC
ADIV
ADLSMP
MODE ADICLK
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ADCx_CFG1 field descriptions
Field Description
31–8
Reserved
This read-only field is reserved and always has the value zero.
7
ADLPC
Low-power configuration
ADLPC controls the power configuration of the successive approximation converter. This optimizes power
consumption when higher sample rates are not required.
Table continues on the next page...
Chapter 32 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 729