Information

ADCx_PGA field descriptions (continued)

Field Description

1000 Reserved

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

1101 Reserved

1110 Reserved

1111 Reserved

15–0

Reserved

This read-only field is reserved and always has the value zero.

32.3.19 ADC minus-side general calibration value register

(ADCx_CLMD)

CLMx contain calibration information that is generated by the calibration function. These

registers contain seven calibration values of varying widths: CLM0[5:0], CLM1[6:0],

CLM2[7:0], CLM3[8:0], CLM4[9:0], CLMS[5:0], and CLMD[5:0]. CLMx are

automatically set once the self calibration sequence is done (CAL is cleared). If these

registers are written by the user after calibration, the linearity error specifications may not

be met.

Addresses: ADC0_CLMD is 4003_B000h base + 54h offset = 4003_B054h

ADC1_CLMD is 400B_B000h base + 54h offset = 400B_B054h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

CLMD

Reset

0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

ADCx_CLMD field descriptions

Field Description

31–6

Reserved

This read-only field is reserved and always has the value zero.

5–0

CLMD

Calibration value

K20 Sub-Family Reference Manual, Rev. 6, Nov 2011

744 Freescale Semiconductor, Inc.