Information

32.3.24 ADC minus-side general calibration value register
(ADCx_CLM1)
For more information, refer to CLMD register description.
Addresses: ADC0_CLM1 is 4003_B000h base + 68h offset = 4003_B068h
ADC1_CLM1 is 400B_B000h base + 68h offset = 400B_B068h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM1
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
ADCx_CLM1 field descriptions
Field Description
31–7
Reserved
This read-only field is reserved and always has the value zero.
6–0
CLM1
Calibration value
32.3.25 ADC minus-side general calibration value register
(ADCx_CLM0)
For more information, refer to CLMD register description.
Addresses: ADC0_CLM0 is 4003_B000h base + 6Ch offset = 4003_B06Ch
ADC1_CLM0 is 400B_B000h base + 6Ch offset = 400B_B06Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CLM0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
ADCx_CLM0 field descriptions
Field Description
31–6
Reserved
This read-only field is reserved and always has the value zero.
5–0
CLM0
Calibration value
Chapter 32 Analog-to-Digital Converter (ADC)
K20 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc. 747